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copyright ? cirrus logic, inc. 2010 (all rights reserved) http://www.cirrus.com fractional-n clock multiplier features ? clock multiplier / jitter reduction ? generates a low jitter 6 - 75 mhz clock from a jittery or intermittent 50 hz to 30 mhz clock source ? highly accurate pll multiplication factor ? maximum error less than 1 ppm in high- resolution mode ? one-time programmability ? configurable hardware control pins ? configurable auxiliary output ? flexible sourcing of reference clock ? external oscillator or clock source ? supports inexpensive local crystal ? minimal board space required ? no external analog loop-filter components general description the cs2100-otp is an extremely versatile system clocking device that utiliz es a programmable phase lock loop. the cs2100-otp is based on a hybrid analog- digital pll architecture comprised of a unique combina- tion of a delta-sigma fractional-n frequency synthesizer and a digital pll. this architecture allows for generation of a low-jitter clock relative to an external noisy synchronization clock with frequencies as low as 50 hz. the cs2100-otp ha s many configuration op- tions which are set once prior to runtime. at runtime there are three hardware configuration pins available for mode and feature selection. the cs2100-otp is available in a 10-pin msop pack- age in commercial (-10c to +70c) and automotive (-40c to +85c) grades. customer development kits are also available for custom device prototyping, small production programming, and device evaluation. please see ?ordering information? on page 26 for com- plete details. hardware configuration auxiliary output 6 to 75 mhz pll output frequency reference 3.3 v hardware control 8 mhz to 75 mhz low-jitter timing reference fractional-n frequency synthesizer digital pll & fractional n logic output to input clock ratio n timing reference pll output lock indicator 50 hz to 30 mhz frequency reference may '10 ds841f2 cs2100-otp
cs2100-otp ds841f2 2 table of contents 1. pin description ............................................................................................................ ..................... 4 2. typical connection diagram ................................................................................................. .... 5 3. characteristics and specificatio ns .......... ................. ................ ................ ................ ........... 6 recommended operating conditions .................................................................................... 6 absolute maximum rating s ............... ................. ................ ................ ............. ............. ............ .. 6 dc electrical characteristics ................................................................................................ 6 ac electrical characteristics ................................................................................................ 7 pll performance plots ......................................................................................................... ...... 8 4. architecture overview ...................................................................................................... ......... 9 4.1 delta-sigma fractional-n fre quency synthesizer ........................................................................... 9 4.2 hybrid analog-digital phase locked loop ....... ............................................................................ ... 9 5. applications ............................................................................................................... .................... 11 5.1 one time programmab ility .................................................................................................. .......... 11 5.2 timing reference clock input .............................................................................................. .......... 11 5.2.1 internal timing re ference clock divider ............................................................................... 11 5.2.2 crystal connections (xti and xto) ............ .......................................................................... 1 2 5.2.3 external reference clock (ref_clk) .................................................................................. 12 5.3 frequency reference clock in put, clk_in ................................................................................... 12 5.3.1 adjusting the minimum loop bandwidth for cl k_in ............................................................ 13 5.4 output to input frequency ratio configuratio n ............................................................................. 14 5.4.1 user defined ratio (rud) ................................................................................................ ..... 14 5.4.2 ratio modifier (r-mod) .................................................................................................. ........ 15 5.4.3 effective ratio (reff) .................................................................................................. ........ 15 5.4.4 ratio configuration summary ..................... ........................................................................ .. 15 5.5 pll clock output .......................................................................................................... ................. 16 5.6 auxiliary output .......................................................................................................... .................... 17 5.7 mode pin functionality .................................................................................................... ............... 17 5.7.1 m1 and m0 mode pin functionality ....................................................................................... 1 7 5.7.2 m2 mode pin functionality ............................................................................................... ..... 18 5.7.2.1 m2 configured as output disable ........ ...................................................................... 18 5.7.2.2 m2 configured as r-mo d enable .............................................................................. 18 5.7.2.3 m2 configured as auxo utsrc override ..................................................................... 18 5.8 clock output stability considerations ..................................................................................... ....... 19 5.8.1 output switching ........................................................................................................ ........... 19 5.8.2 pll unlock conditions ................................................................................................... ....... 19 5.9 required power up sequencing for programmed de vices ........................................................... 19 6. parameter descriptions ..................................................................................................... ...... 20 6.1 modal configuration sets .................................................................................................. ............. 20 6.1.1 r-mod selection (rmodsel[1 :0]) .......................................................................................... .20 6.1.2 auxiliary output source selection (auxouts rc[1:0]) ............................................................. 21 6.2 ratio 0 - 3 ................................................................................................................. ..................... 21 6.3 global configuration parameters ................ ........................................................................... ........ 21 6.3.1 aux pll lock output config uration (auxlockcfg) .............................................................. 21 6.3.2 reference clock input divide r (refclkdiv[1:0]) .................................................................... 21 6.3.3 enable pll clock output on unlock (clkoutunl) ................................................................. 22 6.3.4 low-frequency ratio configuration (lfratiocfg) ................................................................ 22 6.3.5 m2 pin configuration (m2config[2:0]) ................................................................................... 2 2 6.3.6 clock input bandwidth (clk in_bw[2:0]) ................................................................................ 22 7. calculating the user defined ratio .................................................................................... 23 7.1 high resolution 12.20 format .............................................................................................. ......... 23 7.2 high multiplication 20.12 format .......................................................................................... ......... 23 8. programming information .................................................................................................... .... 24
cs2100-otp ds841f2 3 9. package dimensions ......................................................................................................... ........... 25 thermal characteristics ....................................................................................................... .. 25 10. ordering information ...................................................................................................... ........ 26 11. revision history .......................................................................................................... ................ 26 list of figures figure 1. typical connection diagram .......................................................................................... .............. 5 figure 2. clk_in sinusoidal jitt er tolerance .................................................................................. ........... 8 figure 3. clk_in sinusoidal jitter transfer ................................................................................... ............. 8 figure 4. clk_in random jitter re jection and tolerance ........................................................................ .8 figure 5. delta-sigma frac tional-n frequency synthesizer ...................................................................... .9 figure 6. hybrid analog-digital pll ................ ........................................................................... ............... 10 figure 7. internal timing reference clock divider ............................................................................. ...... 11 figure 8. ref_clk frequency vs a fixed clk_out .... .......................................................................... 12 figure 9. external co mponent requirements for crystal circuit .............................................................. 12 figure 10. low bandwidth and new clock domain ................................................................................. ... 13 figure 11. high bandwi dth with clk_in domain re-use ........... ................................................................ 13 figure 12. ratio feature summary .............................................................................................. ............. 16 figure 13. pll clock output options ........................................................................................... ............ 16 figure 14. auxiliary output sele ction ......................................................................................... ............... 17 figure 15. m2 mapping options ................................................................................................. ............... 18 figure 16. parameter conf iguration sets ....................................................................................... ........... 20 list of tables table 1. modal and global configuration ....................................................................................... ........... 11 table 2. ratio modifier ....................................................................................................... ....................... 15 table 3. example 12.20 r-values ............................................................................................... ............. 23 table 4. example 20.12 r-values ............................................................................................... ............. 23
cs2100-otp 4 ds841f2 1. pin description pin name # pin description vd 1 digital power ( input ) - positive power supply for the digital and analog sections. gnd 2 ground ( input ) - ground reference. clk_out 3 pll clock output ( output ) - pll clock output. aux_out 4 auxiliary output ( output ) - this pin outputs a buffered version of one of the input or output clocks, or a status signal, depending on configuration. clk_in 5 frequency reference clock input ( input ) - clock input for the digital pll frequency reference. xto xti/ref_clk 6 7 crystal connections (xti/xto) / timing reference clock input (ref_clk) ( input/output ) - xti/xto are i/o pins for an external crystal whic h may be used to generate the low-jitter pll input clock. ref_clk is an input for an externa lly generated low-jitter reference clock. m2 8 mode select ( input ) - m2 is a configurable mode selection pin. m1 9 mode select ( input ) - m1 is a configurable mode selection pin. m0 10 mode select ( input ) - m0 is a configurable mode selection pin. 1 2 3 4 5 6 7 8 9 10 xto clk_out gnd vd xti/ref_clk m2 m1 m0 aux_out clk_in
cs2100-otp ds841f2 5 2. typical conn ection diagram 2 1 gnd m2 m1 xti/ref_clk frequency reference clk_in xto clk_out aux_out 0.1 f vd +3.3 v m0 low-jitter timing reference system microcontroller 1 f 1 or 2 ref_clk xto xti xto or 40 pf x 40 pf crystal to circuitry which requires a low-jitter clock n.c. to other circuitry or microcontroller figure 1. typical connection diagram cs2100-otp
cs2100-otp 6 ds841f2 3. characteristics an d specifications recommended operating conditions gnd = 0 v; all voltages with respect to ground. ( note 1 ) notes: 1. device functionality is not guaranteed or implied ou tside of these limits. operat ion outside of these limits may adversely affect device reliability. 2. clk_in must not be applied when these conditions are not met, including during power up. see section 5.9 on page 19 for required power up procedure. absolute maximum ratings gnd = 0 v; all voltages with respect to ground. warning: operation at or beyond these limits may result in permanent damage to the device. notes: 3. the maximum over/under voltage is limited by the input current except on the power supply pin. dc electrical characteristics test conditions (unless otherwise specified): vd = 3.1 v to 3.5 v; t a = -10c to +70c (commercial grade); t a = -40c to +85c (automotive grade). notes: 4. to calculate the additional curr ent consumption due to loading (per output pin), multiply clock output frequency by load capacitance and power supply voltage. for example, f clk_out (49.152 mhz) * c l (15 pf) * vd (3.3 v) = 2.4 ma of additional current due to these loading conditions on clk_out. parameters symbol min typ max units dc power supply ( note 2 ) vd 3.1 3.3 3.5 v ambient operating temper ature (power applied) commercial grade automotive grade t ac t ad -10 -40 - - +70 +85 c c parameters symb ol min max units dc power supply vd -0.3 6.0 v input current i in -10ma digital input voltage ( note 3 )v in -0.3 vd + 0.4 v ambient operating temper ature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units power supply current - unloaded ( note 4 )i d -1218ma power dissipation - unloaded ( note 4 )p d -4060mw input leakage current i in --10a input capacitance i c -8-pf high-level input voltage v ih 70% - - vd low-level input voltage v il --30%vd high-level output voltage (i oh = -1.2 ma) v oh 80% - - vd low-level output voltage (i oh = 1.2 ma) v ol --20%vd
cs2100-otp ds841f2 7 ac electrical characteristics test conditions (unless otherwise sp ecified): vd = 3.1 v to 3.5 v; t a = -10c to +70c (commercial grade); t a = -40c to +85c (automotive grade); c l =15pf. notes: 5. 1 ui (unit interval) corresponds to t sys_clk or 1/f sys_clk . 6. f clk_out = 24.576 mhz; sample size = 10,000 points; auxoutsrc[1:0] =11. 7. in accordance with aes-12id-2006 section 3.4.2. measurements are time interv al error taken with 3rd order 100 hz to 40 khz bandpass filter. 8. in accordance with aes-12id-2006 section 3.4.1. measurements are time interv al error taken with 3rd order 100 hz highpass filter. 9. 1 ui (unit interval) corresponds to t clk_in or 1/f clk_in . 10. the frequency accuracy of the pll clock output is di rectly proportional to the frequency accuracy of the reference clock. parameters symbol conditions min typ max units crystal frequency fundamental mode xtal f xtal refclkdiv[1:0] = 10 refclkdiv[1:0] = 01 refclkdiv[1:0] = 00 8 16 32 - - - 18.75 37.5 50 mhz mhz mhz reference clock input frequency f ref_clk refclkdiv[1:0] = 10 refclkdiv[1:0] = 01 refclkdiv[1:0] = 00 8 16 32 - - - 18.75 37.5 75 mhz mhz mhz reference clock input duty cycle d ref_clk 45 - 55 % internal system clock frequency f sys_clk 8 18.75 mhz clock input frequency f clk_in 50 hz - 30 mhz clock input pulse width ( note 5 )pw clk_in f clk_in < f sys_clk /96 f clk_in > f sys_clk /96 2 10 - - - - ui ns pll clock output frequency f clk_out 6-75mhz pll clock output duty cycle t od measured at vd/2 45 50 55 % clock output rise time t or 20% to 80% of vd - 1.7 3.0 ns clock output fall time t of 80% to 20% of vd - 1.7 3.0 ns period jitter t jit ( note 6 ) - 70 - ps rms base band jitter (100 hz to 40 khz) (notes 6 , 7 ) - 50 - ps rms wide band jitter (100 hz corner) (notes 6 , 8 ) - 175 - ps rms pll lock time - clk_in ( note 9 )t lc f clk_in < 200 khz f clk_in > 200 khz - - 100 1 200 3 ui ms pll lock time - ref_clk t lr f ref_clk = 8 to 75 mhz - 1 3 ms output frequency synthesis resolution ( note 10 )f err high resolution high multiplication 0 0 - - 0.5 112 ppm ppm
cs2100-otp 8 ds841f2 pll performance plots test conditions (unless otherwise specified): vd = 3.3 v; t a =25c; c l =15pf; f clk_out = 12.288 mhz; f clk_in = 12.288 mhz; sample size = 10,000 points; base band jitter (100 hz to 40 khz); auxoutsrc[1:0] =11. 1 10 100 1,000 10,000 0.1 1 10 100 1,000 10,000 input jitter frequency (hz) max input jitter level (usec) 1 hz bandwidth 128 hz bandwidth 1 10 100 1000 10000 -60 -50 -40 -30 -20 -10 0 10 input jitter frequency (hz) jitter transfer (db) 1 hz bandwidth 128 hz bandwidth figure 2. clk_in sinusoidal jitter toleranc e figure 3. clk_in sinusoidal jitter transfer samples size = 2.5m points; base band jitter (10hz to 40khz). samples size = 2.5m points; base band jitter (10hz to 40khz). figure 4. clk_in random jitter rejection and tolerance 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 input jitter level (nsec) output jitter level (nsec) 1 hz bandwidth 128 hz bandwidth unlock unlock
cs2100-otp ds841f2 9 4. architecture overview 4.1 delta-sigma fractional- n frequency synthesizer the core of the cs2100 is a delta-sigma fractional-n frequency synthesizer which has very high-resolu- tion for input/output cloc k ratios, low phase noise, very wide ran ge of output frequencies and the ability to quickly tune to a new frequency. in very simplistic te rms, the fractional-n frequency synthesizer multiplies the timing reference clock by the value of n to generate the pll out put clock. the desired output to input clock ratio is the value of n that is a pplied to the delta-sigma modulator (see figure 5 ). the analog pll based frequency synthesizer uses a low-jitter timing reference clock as a time and phase reference for the inte rnal voltage controlled oscilla tor (vco). the phase compar ator compares the fraction- al-n divided clock with the original timing reference and generates a control signal. the control signal is fil- tered by the internal loop filter to generate the vco?s control voltage wh ich sets its output frequency. the delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the reference clock and the vco output (thus the duty cycl e of the modulator sets the fractional value). this allows the design to be optimized fo r very fast lock times for a wide range of output frequencies without the need for external filter components. as with any frac tional-n frequency synthe sizer the timing reference clock should be stable and jitter-free. figure 5. delta-sigma fractional-n frequency synthesizer 4.2 hybrid analog-digital phase locked loop the addition of the digital pll and fractional-n logic (shown in figure 6 ) to the fractional-n frequency synthesizer creates the hybrid analog-digital phase locked loop with many advantages over classical an- alog pll techniques. these advantages in clude the ability to operate over extremely wide frequency ranges without the need to change external loop filter comp onents while maintaining impr essive jitter reduction per- formance. in the hybrid architecture, the digital pll ca lculates the ratio of the pll output clock to the fre- quency reference and compares that to the desired rati o. the digital logic genera tes a value of n which is then applied to the fractional-n frequency synthesizer to generate the desired pll output frequency. notice that the frequency and phase of the timing reference signal do not affect the ou tput of the pll since the digital control loop will correc t for the pll output. a majo r advantage of the digital pll is the ease with which the loop filter bandwidth can be altered. the pll band width is set to a wide-ba ndwidth mode to quickly achieve lock and then reduced for optimal jitter rejection. fractional-n divider timing reference clock pll output voltage controlled oscillator internal loop filter phase comparator n delta-sigma modulator
cs2100-otp 10 ds841f2 figure 6. hybrid analog-digital pll n digital filter frequency comparator for frac-n generation frequency reference clock delta-sigma fractional-n frequency synthesizer digital pll and fractional-n logic output to input ratio for hybrid mode fractional-n divider timing reference clock pll output voltage controlled oscillator internal loop filter phase comparator delta-sigma modulator
cs2100-otp ds841f2 11 5. applications 5.1 one time programmability the one time programmable (otp) circuitry in the cs2 100-otp allows for pre-configuration of the device prior to use in a system. there are two types of para meters that are used for device pre-configuration: modal and global . the modal parameters are features which, when grou ped together, create a modal configuration set (see figure 16 on page 20 ). up to four modal configuration se ts can be permanently stored and then dynamically selected using the m[ 1:0] mode select pins (see table 1 ). the global parameters are the re- maining configuration settings which do not change wit h the mode select pins. the modal and global pa- rameters can be pre-set at the factory or user programmed using the customer development kit, cdk2000; please see ?programming information? on page 24 for more details. table 1. modal and global configuration 5.2 timing reference clock input the low jitter timing reference clock (refclk) can be pr ovided by either an external reference clock or an external crystal in conjunction with t he internal oscillator. in order to ma intain a stable and low-jitter pll out- put the timing reference clock must also be stable and low-jitter; the qu ality of the timing reference clock directly affects the performance of the pl l and hence the quality of the pll output. 5.2.1 internal timing reference clock divider the internal timing reference clock (sysclk) is limited to a lower ma ximum frequency than that allowed on the xti/ref_clk pin. the cs2100-otp supports the wider external frequency range by offering an internal divider for refclk. the refclkdiv[1:0] global parameter should be configured such that sysclk, the divided refclk, then falls within the valid range as indicated in ?ac electrical characteristics? on page 7 . it should be noted that the maximum allowable in put frequency of the xti/ref_clk pin is dependent upon its configuration as either a crystal connection or external clock input. see the ?ac electrical char- acteristics? on page 7 for more details. for the lowest possible output jitter, attention should be paid to the absolute frequency of the timing ref- erence clock relative to the pll output frequency (c lk_out). to minimize outpu t jitter, the timing ref- erence clock frequency should be chosen such that f refclk is at least +/-15 khz from f clk_out *n/32 where n is an integer. figure 8 shows the effect of varying the refclk frequency around f clk_out *n/32. it should be noted that there will be a jitter null at the zero point when n = 32 (not shown in figure 8 ). an parameter type m[1:0] pins = 00 m[1:0] pins = 01 m[1:0] pins = 10 m[1:0] pins = 11 modal configuration set 0 ratio 0 configuration set 1 ratio 1 configuration set 2 ratio 2 configuration set 3 ratio 3 global configuration settings set once for all modes. figure 7. internal timing reference clock divider n internal timing reference clock pll output fractional-n frequency synthesizer timing reference clock divider 1 2 4 xti/ref_clk refclkdiv[1:0] 8 mhz < sysclk < 18.75 mhz 8 mhz < refclk < timing reference clock 50 mhz (xti) 75 mhz (ref_clk)
cs2100-otp 12 ds841f2 example of how to determine the range of refclk frequencies around 12 mhz to be used in order to achieve the lowest jitter pll output at a frequency of 12.288 mhz is as follows: where: and 5.2.2 crystal connections (xti and xto) an external crystal may be used to generate refclk . to accomplish this, a 20 pf fundamental mode par- allel resonant crystal must be connected between the xti and xto pins as shown in figure 9 . as shown, nothing other than the crystal and its load capacitors should be connected to xti and xto. please refer to the ?ac electrical characteristics? on page 7 for the allowed crystal frequency range. 5.2.3 external reference clock (ref_clk) for operation with an externally generated ref_cl k signal, xti/ref_clk should be connected to the reference clock source and xto should be left unconnected or terminated through a 47 k resistor to gnd. 5.3 frequency reference clock input, clk_in the frequency reference clock input (clk_in) is used by the digital pll and fractional-n logic block to dynamically generate a fractional-n va lue for the frequency synthesizer (see ?hybrid analog-digital pll? on page 10 ). the digital pll first compares the clk_in frequency to the pll output. the fractional-n logic block then translates the desired ratio based off of clk_in to one based off of the internal timing reference referenced control parameter definition refclkdiv[1:0] ....................... ?reference clock input divider (refclkdiv[1:0])? on page 21 -80 -60 -40 -20 0 20 40 60 80 20 40 60 80 100 120 140 160 180 normalized ref__clk frequency (khz) typical base band jitter (psec) clk__out jitter -15 khz +15 khz clk__out f *32/n figure 8. ref_clk frequency vs. a fixed clk_out f l f refclk f h ? f l f clk_out 31 32 ----- - 15 khz + = 12.288 mhz 0.96875 15 khz + = 11.919 mhz = f h f clk_out 32 32 ----- - 15 khz ? = 12.288 mhz 115 khz + = 12.273 mhz = xti xto 40 pf 40 pf figure 9. external component requirements for crystal circuit
cs2100-otp ds841f2 13 clock (sysclk). this allows the low-jitter timing refe rence clock to be used as the clock which the frequency synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the digital pll. the allowable frequency range for clk_in is found in the ?ac electrical characteristics? on page 7 . 5.3.1 adjusting the minimum loop bandwidth for clk_in the cs2100 allows the minimum loop bandwidth of the digital pll to be adjusted between 1 hz and 128 hz using the clkin_bw[2:0] global parameter. the minimum loop bandwidth of the digital pll direct- ly affects the jitter transfer function; specifically, jit ter frequencies below the loop bandwidth corner are passed from the pll input directly to the pll output without attenuation. in some applications it is desir- able to have a very low minimum loop bandwidth to re ject very low jitter freque ncies, commonly referred to as wander. in others it may be preferable to remove only higher frequency jitter, allowing the input wan- der to pass through the pll without attenuation. typically, applications in which the pll_out signal creates a new clock domain from which all other sys- tem clocks and associated data ar e derived will benefit from the maxi mum jitter and wander rejection of the lowest pll bandwidth setting. see figure 10 . systems in which some clocks and data are derived from the pll_out signal while other clocks and data are derived from the clk_in signal will often require phase alignment of all the clocks and data in the system. see figure 11 . if there is substantial wander on the clk_ in signal in these applications, it may be necessary to increase the minimum loop bandwid th allowing this wander to pass through to the clk_out signal in order to maintain phase alignment. for these applications, it is advised to experiment with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing errors due to wandering between the clocks and data synchronous to the clk_in domain and those synchronous to the pll_out domain. figure 10. low bandwidt h and new clock domain lrck sclk sdata mclk mclk wander > 1 hz wander and jitter > 1 hz rejected d0 d1 lrck sclk sdata subclocks generated from new clock domain. or pll bw = 1 hz clk_in pll_out d0 d1 jitter figure 11. high bandwidth with clk_in domain re-use d0 d1 lrck sclk sdata mclk mclk wander < 128 hz jitter > 128 hz rejected wander < 128 hz passed to output lrck sclk sdata or pll bw = 128 hz clk_in pll_out subclocks and data re-used from previous clock domain. jitter d0 d1
cs2100-otp 14 ds841f2 while acquiring lock, the digital lo op bandwidth is automatically se t to a large valu e. once lock is achieved, the digital loop bandwidth will settl e to the minimum valu e selected by the clkin_bw[2:0] pa- rameter. 5.4 output to input freque ncy ratio configuration 5.4.1 user defined ratio (r ud ) the user defined ratio, r ud , is a 32-bit un-signed fixed-point numb er which determines the basis for the desired input to output clock ratio. up to four different ratios, ratio 0-3 , can be stored in the cs2100?s one time programmable memory. selection between the four ratios is achieved by the m[1:0] mode select pins. the 32-bit r ud can be expressed in either a high resolu tion (12.20) or high multiplication (20.12) format selectable by the lfratiocfg global parameter. the r ud for high resolution (12.20) format is encoded with 12 msbs representing the integer binary por- tion with the remaining 20 lsbs representing the frac tional binary portion. the maximum multiplication factor is approximately 4096 with a resolution of 0.954 ppm in this configuration. see ?calculating the user defined ratio? on page 23 for more information. the r ud for high multiplication (20.12) format is encod ed with 20 msbs representing the integer binary portion with the remaining 12 lsbs representing the frac tional binary portion. in this configuration, the maximum multiplication factor is approximately 1,048,575 with a resolution of 244 ppm. it is recommend- ed that the 12.20 high-reso lution format be utilized whenever the desired ratio is less than 4096 since the output frequency accuracy of the pll is directly proportional to the accuracy of the timing reference clock and the resolution of the r ud . the status of internal dividers, such as the internal timing reference clock divider, are automatically taken into account. therefore r ud is simply the desired ratio of th e output to input clock frequencies. referenced control parameter definition clkin_bw[2:0] ....................... ?clock input bandwidth (clkin_bw[2:0])? on page 22 referenced control parameter definition ratio 0-3................................ ?ratio 0 - 3? on page 21 lfratiocfg ............................ ?low-frequency ratio configuration (lfratiocfg)? on page 22 m[1:0] .................................... ?m1 and m0 mode pin functionality? on page 17
cs2100-otp ds841f2 15 5.4.2 ratio modifier (r-mod) the ratio modifier is used to internally multiply/divide the currently addressed r ud ( ratio 0-3 stored in the register space remain unchanged). the available options for r-mod are summarized in table 2 on page 15 . r-mod is enabled via the m2 pin in conj unction with the appropriate setting of the m2config[2:0] global parameter (see section 5.7.2 on page 18 ). table 2. ratio modifier 5.4.3 effective ratio (r eff ) the effective ratio (r eff ) is an internal calculation comprised of r ud and the appropriate modifiers, as previously described. r eff is calculated as follows: r eff = r ud ? r-mod to simplify operation the device handles some of th e ratio calculation functi ons automatically (such as when the internal timing reference clock divider is se t). for this reason, the ef fective ratio does not need to be altered to account for internal dividers. ratio modifiers which would produce an overflow or truncation of r eff should not be used. in all cases, the maximum and minimum allowable values for r eff are dictated by the fr equency limits for both the input and output clocks as shown in the ?ac electrical charac teristics? on page 7 . selection of the user defined ratio from the four stored ratios is made by using the m[1:0] pins. 5.4.4 ratio configuration summary the r ud is the user defined ratio for whic h up to four different values ( ratio 0-3 ) can be stored in the one time programmable memory. the m[1:0] pins then select the user defined ratio to be used as well as the modal configuration set. the resolution/format for the r ud is selectable. r-mod is applied accordingly. the user defined ratio, ratio modifier, and automa tic ratio modifier make up the effective ratio r eff , the rmodsel[1:0] r modifier 00 0.5 01 0.25 10 0.125 11 0.0625 referenced control parameter definition ratio 0-3................................ ?ratio 0 - 3? on page 21 rmodsel[1:0] ........................ ?r-mod selection (rmodsel[1:0])? section on page 20 m2config[2:0]........................ ?m2 pin configuration (m2config[2:0])? on page 22 referenced control parameter definition m[1:0] pins............................. ?m1 and m0 mode pin functionality? on page 17
cs2100-otp 16 ds841f2 final calculation used to determine the output to input clock ratio. the effective ratio is then corrected for the internal dividers. the conceptual diagram in figure 12 summarizes the features involved in the calcu- lation of the ratio values used to generate the frac tional-n value which contro ls the frequency synthesiz- er. the subscript ?4? indicates the modal parameters. figure 12. ratio feature summary 5.5 pll clock output the pll clock output pin (clk_out) provides a buffered version of the output of the frequency synthesizer. the driver can be set to high-impedance with the m2 pin when the m2config[1:0] global parameter is set to either 000 or 010. the output from the pll automatica lly drives a static low c ondition while the pll is un- locked (when the clock may be unreliable). this feature can be disabled by setting the clkoutunl global parameter, however the state clk_out may then be unreliable during an unlock condition. figure 13. pll clock output options referenced control parameter definition ratio 0-3................................ ?ratio 0 - 3? on page 21 m[1:0] pins............................. ?m1 and m0 mode pin functionality? on page 17 lfratiocfg ............................ ?low-frequency ratio configuration (lfratiocfg)? on page 22 rmodsel[1:0] ........................ ?r-mod selection (rmodsel[1:0])? section on page 20 refclkdiv[1:0] ....................... ?reference clock input divider (refclkdiv[1:0])? on page 21 referenced control parameter definition clkoutunl.............................. ?enable pll clock output on unlock (clkoutunl)? on page 22 clkoutdis .............................. ?m2 configured as output disable? on page 18 m2config[2:0]........................ ?m2 pin configuration (m2config[2:0])? on page 22 effective ratio r eff ratio format frequency reference clock (clk_in) sysclk pll output frequency synthesizer digital pll & fractional n logic ratio 0 ratio 1 ratio 2 ratio 3 12.20 20.12 m[1:0] pins lfratiocfg rmodsel[1:0] 4 ratio modifier r correction refclkdiv[1:0] timing reference clock (xti/ref_clk) divide refclkdiv[1:0] dynamic ratio, ?n? user defined ratio r ud m2 pin pll locked/unlocked pll output 2:1 mux m2 pin with m2config[1:0] = 000, 010 2:1 mux clkoutunl 0 pll clock output pin (clk_out) 0 1 0 1 pll clock output pllclkout
cs2100-otp ds841f2 17 5.6 auxiliary output the auxiliary output pin (aux_out ) can be mapped, as shown in figure 14 , to one of four signals: refer- ence clock (refclk), input clock (clk_i n), additional pll clock output (clk_out), or a pll lock indicator (lock). the mux is controlled via the auxoutsrc[1:0] modal parameter. if aux_ out is set to lock, the aux- lockcfg global parameter is then used to control the output driver type an d polarity of the lock signal (see section 6.3.1 on page 21 ). if aux_out is set to clk_out, the phase of the pll clo ck output signal on aux_out may differ from the clk_out pin. the driver for the pin can be set to high-impedance using the m2 pin when the m2config[1:0] global parameter is set to either 001 or 010. figure 14. auxiliary output selection 5.7 mode pin functionality 5.7.1 m1 and m0 mode pin functionality m[1:0] determine the functional mode of the device and select both the default user defined ratio and the set of modal parameters. the modal parameters are rmodsel[1:0] , and auxoutsrc[1:0] . by modifying one or more of the modal parameters between the 4 sets, different functional configurations can be achieved. however, global parame ters are fixed and the same val ue will be applied to each functional configuration. figure 16 on page 20 provides a summary of all parameters used by the device. referenced control parameter definition auxoutsrc[1:0]...................... ?auxiliary output source selection (auxoutsrc[1:0])? on page 21 auxoutdis ............................. ?m2 configured as output disable? on page 18 auxlockcfg........................... ?aux pll lock output configuration (auxlockcfg)? section on page 21 m2config[2:0]........................ ?m2 pin configuration (m2config[2:0])? on page 22 frequency reference clock (clk_in) pll lock/unlock indication (lock) timing reference clock (refclk) pll clock output (pllclkout) 4:1 mux auxiliary output pin (aux_out) auxoutsrc[1:0] auxlockcfg m2 pin with m2config[1:0] = 001, 010
cs2100-otp 18 ds841f2 5.7.2 m2 mode pin functionality m2 usage is mapped to one of the optional special functions via the m2config[2:0] global parameter. de- pending on what m2 is mapp ed to, it will either act as an output en able/disable pin or override certain mod- al parameters. figure 15 summarizes the available options and the following se ctions will describe each option in more detail. figure 15. m2 mapping options 5.7.2.1 m2 configured as output disable if m2config[2:0] is set to either ?000?, ?0 01?, or ?010?, m2 becomes an output disable pin for one or both output pins. if m2 is driven ?low?, the corresponding output(s ) will be enabled, if m2 is driven ?high?, the corresponding output(s) will be disabled. 5.7.2.2 m2 configured as r-mod enable if m2config[2:0] is set to ?011?, m2 becomes the r-mod enable pin. it should be noted that m2 is the only way to enable r-mod. even though the rmodsel[1:0] modal parameter can be set arbi- trarily for each configuration set, it will not take effect unless enabled via m2. if m2 is driven ?low?, r-mod will be disabled, if m2 is dr iven ?high? r-mod will be enabled. 5.7.2.3 m2 configured as auxoutsrc override if m2config[2:0] is set to ?111?, m2 when dr iven ?high? will override the auxoutsrc[1:0] modal pa- rameter and force the aux_out source to pll clo ck output. when m2 is driven ?low?, aux_out will function according to auxoutsrc[1:0] . m2 pin disable clk_out and aux_out pins disable aux_out pin disable clk_out pin rmodsel[1:0] modal parameter enable force auxoutsel[1:0] = 10 (pll clock out) reserved m2config[2:0] global parameter 000 001 010 011 100 101 110 111 reserved reserved
cs2100-otp ds841f2 19 5.8 clock output stability considerations 5.8.1 output switching the cs2100-otp is designed such that re-configuratio n of the clock routing func tions do not result in a partial clock period on any of the active outputs (clk_out and/or aux_out). in particular, enabling or disabling an output, changing th e auxiliary output source between ref_clk and clk_ out, and the au- tomatic disabling of th e output(s) during unlo ck will not cause a runt or partial clock period. the following exceptions/limitations exist: ? enabling/disabling aux_out when auxoutsrc[1:0] = 11 (unlock indicator). ? switching auxoutsrc[1:0] to or from 01 (clk_in) and to or from 11 (unlock indicator) (transitions between auxoutsrc[1:0] = [00,10] will not produce a glitch). when any of these exceptions occur, a part ial clock period on the output may result. 5.8.2 pll unlock conditions certain changes to the clock inputs and mode pins can cause the pll to lose lock which will affect the presence of a clock signal on cl k_out. the following outlines which conditions cause the pll to go un- locked: ? any change in the state of the m1 and m0 pins will cause the pll to temporarily lose lock as the new setting takes affect. ? changes made to the state of the m2 when the m2config[2:0] global parameter is set to 011, 100, 101, or 110 can cause the pll to temporarily lose lock as the new setting takes affect. ? any discontinuities on the ti ming reference clock, ref_clk. ? discontinuities on the frequency reference clock, clk_in. ? gradual changes in clk_in frequency great er than 30% from the starting frequency. ? step changes in clk_in frequency. 5.9 required power up seque ncing for programmed devices ? apply power. all input pins, except xti/ref_clk, should be held in a static logic hi or lo state until the dc power supply specification in the ?recommended operating conditions? table on page 6 are met. ? apply input clock(s) if required. ? for cdk programmed devices, toggle the state of the m0, m1, or both pins at least 3 times to initialize the device. this must be done after the power supply is stable and before normal operation is expected. note: this operation is not required for factory programmed devices. ? after the specified pll lock time on page 7 has passed, the device will outp ut the desired clock as con- figured by the m0-m2 pins.
cs2100-otp 20 ds841f2 6. parameter descriptions as mentioned in section 5.1 on page 11 , there are two different kinds of parameter configuration sets, modal and global. these configuration sets, shown in figure 16 , can be programmed in the field using the cdk2000 or pre- programmed at the factory. please see ?programming information? on page 24 for more details. figure 16. parameter configuration sets 6.1 modal configuration sets there are four instances of each of these configuration param eters. selection between the four stored sets is made using the m[1:0] pins. 6.1.1 r-mod selection (rmodsel[1:0]) selects the r-mod value, which is used as a fa ctor in determining the pll?s fractional n. note: this parameter does not take affect unless m2 pin is high and the m2config[2:0] global param- eter is set to ?011?. rmodsel[1:0] r-mod selection 00 right-shift r-value by 1 ( 2). 01 right-shift r-value by 2 ( 4). 10 right-shift r-value by 3 ( 8). 11 right-shift r-value by 4 ( 16). application: ?ratio modifier (r-mod)? on page 15 m[1:0] pins modal configuration set #0 rmodsel[1:0] auxoutsrc[1:0] modal configuration set #1 ratio 1 rmodsel[1:0] auxoutsrc[1:0] modal configuration set #2 ratio 2 rmodsel[1:0] auxoutsrc[1:0] modal configuration set #3 ratio 3 rmodsel[1:0] auxoutsrc[1:0] 00 01 10 11 global configuration set refclkdiv[1:0] clkoutunl auxlockcfg lfratiocfg m2config[2:0] ratio 0 digital/pll core clkin_bw[2:0]
cs2100-otp ds841f2 21 6.1.2 auxiliary output sour ce selection (auxoutsrc[1:0]) selects the source of the aux_out signal. note: when set to 11, the auxlockcfg global parameter sets the polarity and driver type ( ?aux pll lock output configuration (auxlockcfg)? on page 21 ). 6.2 ratio 0 - 3 the four 32-bit user defined ratios are stored in the cs2100?s one time programmable memory. see ?out- put to input frequency ratio configuration? on page 14 and ?calculating the user defined ratio? on page 23 for more details. 6.3 global configuration parameters 6.3.1 aux pll lock output configuration (auxlockcfg) when the aux_out pin is configured as a lock indicator ( auxoutsrc[1:0] modal parameter = ?11?), this global parameter configures the aux_ out driver to either push-pull or open drain. it also determines the polarity of the lock signal. if aux_ out is configured as a clock output, the state of this parameter is dis- regarded. note: aux_out is an un lock indicator, signalling an error condition when the pll is unlocked. there- fore, the pin polarity is defined relative to the un lock condition. 6.3.2 reference clock input divider (refclkdiv[1:0]) selects the input divider for the timing reference clock. auxoutsrc[1:0] auxiliary output source 00 refclk. 01 clk_in. 10 clk_out. 11 pll lock status indicator. application: ?auxiliary output? on page 17 auxlockcfg aux_out driver configuration 0 push-pull, active high (output ?high? for unlocked condition, ?low? for locked condition). 1 open drain, active low (output ?low? for unl ocked condition, high-z for locked condition). application: ?auxiliary output? on page 17 refclkdiv[1:0] reference clock input divider ref_clk frequency range 00 4. 32 mhz to 75 mhz (50 mhz with xti) 01 2. 16 mhz to 37.5 mhz 10 1. 8 mhz to 18.75 mhz 11 reserved. application: ?internal timing reference clock divider? on page 11
cs2100-otp 22 ds841f2 6.3.3 enable pll clock out put on unlock (clkoutunl) defines the state of the pll output during the pll unlock condition. 6.3.4 low-frequency ratio configuration (lfratiocfg) determines how to interpret the currentl y indexed 32-bit user defined ratio. 6.3.5 m2 pin configur ation (m2config[2:0]) controls which special function is mapped to the m2 pin . 6.3.6 clock input bandwidth (clkin_bw[2:0]) sets the minimum loop bandwidth when locked to clk_in. clkoutunl clock output enable status 0 clock outputs are driven ?low? when pll is unlocked. 1 clock outputs are always enabled (results in unpredictable output when pll is unlocked). application: ?pll clock output? on page 16 lfratiocfg ratio bit encoding interpretation 0 20.12 - high multiplier. 1 12.20 - high accuracy. application: ?user defined ratio (rud)? on page 14 m2config[2:0] m2 pin function 000 disable clk_out pin. 001 disable aux_out pin. 010 disable clk_out and aux_out. 011 rmodsel[1:0] modal parameter enable. 100 reserved. 101 reserved. 110 reserved. 111 force auxoutsrc[1:0] = 10 (pll clock out). application: ?m2 mode pin functionality? on page 18 clkin_bw[2:0] minimum loop bandwidth 000 1 hz 001 2 hz 010 4 hz 011 8 hz 100 16 hz 101 32 hz 110 64 hz 111 128 hz application: ?adjusting the minimum loop bandwidth for clk_in? on page 13
cs2100-otp ds841f2 23 7. calculating the us er defined ratio note: the software for use with the evaluation kit has built in tools to aid in calculating and converting the user defined ratio. this section is for those who would lik e to know more about how the user defined ratio is calculated and stored. most calculators do not interpret the fixed point binary representation which the cs2100-otp uses to define the output to input clock ratio (see section 5.4.1 on page 14 ); however, with a simple c onversion we can use these tools to generate a binary or hex value for ratio 0-3 to be stored in one time programmable memory. please see ?program- ming information? on page 24 for more details on programming. 7.1 high resolution 12.20 format to calculate the user defined ratio (r ud ) to store in the register(s), divi de the desired output clock frequen- cy by the given input clock (clk_in). then multip ly the desired ratio by the scaling factor of 2 20 to get the scaled decimal representation; then use the decimal to binary /hex conversion function on a calculator and write to the register. a few examples have been provided in table 3 . table 3. example 12.20 r-values 7.2 high multiplication 20.12 format to calculate the user defined ratio (r ud ) to store in the register(s), divi de the desired output clock frequen- cy by the given input clock (clk_in). then multip ly the desired ratio by the scaling factor of 2 12 to get the scaled decimal representation; then use the decimal to binary /hex conversion function on a calculator and write to the register. a few examples have been provided in table 4 . table 4. example 20.12 r-values desired output to input clock ratio (output clock/input clock) scaled decimal representation = (output clock/input clock) ? 2 20 hex representation of binary r ud 12.288 mhz/10 mhz=1.2288 1288490 00 13 a9 2a 11.2896 mhz/44.1 khz=256 268435456 10 00 00 00 desired output to input clock ratio (output clock/input clock) scaled decimal representation = (output clock/input clock) ? 2 12 hex representation of binary r ud 12.288 mhz/60 hz=204,800 838860800 32 00 00 00 11.2896 mhz/59.97 hz =188254.127... 771088904 2d f5 e2 08
cs2100-otp 24 ds841f2 8. programming information field programming of the cs2100-otp is achieved using the hardware and software tools included with the cdk2000. the software tools can be downloaded from www.cirrus.com for evaluation prior to ordering a cdk. the cdk2000 is designed with built-in features to ease the process of programming small quantities of devices for pro- totype and small production builds. in addition to its fi eld programming capabilities, the cdk2000 can also be used for the complete evaluation of programmed cs2100-otp devices. the cs2100-otp can also be factory programmed for la rge quantity orders. when ordering factory programmed devices, the cdk should first be used to program and eval uate the desired configuration. when evaluation is com- plete, the cs2000 configuration wizard is used to genera te a file containing all device configuration information; this file is conveyed to cirrus logic as a complete sp ecification for the factory prog ramming configuration. please contact your local cirrus lo gic sales representative for more information regarding factory programmed parts. see the cdk2000 datasheet, available at www.cirrus.com , for detailed information on the use of the cdk2000 pro- gramming and evaluation tools. below is a form which represents the information required for programming a device (noted in gray). the ?parameter descriptions? section beginning on page 20 describes the functions of each parameter. this form may be used ei- ther for personal notation for device configuration or it can be filled out and given to a cirrus representative in con- junction with the programming file from the cdk2000 as an additional check. the user defined ratio may be filled out in decimal or it may be entered as hex as outlined in ?calculating the user defined ratio? on page 23 . for all other parameters mark a ?0? or ?1? below the parameter name. otp modal and global config uration parameters form modal configuration set #0 ratio 0 (dec) ratio 0 (hex) __ __ : __ __ : __ __ : __ __ rmodsel1 rmodsel0 auxoutsrc1 auxoutsrc0 modal configuration set #1 ratio 1 (dec) ratio 1 (hex) __ __ : __ __ : __ __ : __ __ rmodsel1 rmodsel0 auxoutsrc1 auxoutsrc0 modal configuration set #2 ratio 2 (dec) ratio 2 (hex) __ __ : __ __ : __ __ : __ __ rmodsel1 rmodsel0 auxoutsrc1 auxoutsrc0 modal configuration set #3 ratio 3 (dec) ratio 3 (hex) __ __ : __ __ : __ __ : __ __ rmodsel1 rmodsel0 auxoutsrc1 auxoutsrc0 global configuration set auxlockcfg refclkdiv1 refclkdiv0 clkout unl lfratiocfg m2cfg2 m2cfg1 m2cfg0 clkin_bw2 clkin_bw1 clkin_bw0
cs2100-otp ds841f2 25 9. package dimensions notes: 1. reference document: jedec mo-187 2. d does not include mold flash or prot rusions which is 0.15 mm max. per side. 3. e1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. dimension b does not include a total allo wable dambar protrusion of 0.08 mm max. 5. exceptions to jedec dimension. thermal characteristics inches millimeters note dim min nom max min nom max a -- -- 0.0433 -- -- 1.10 a1 0 -- 0.0059 0 -- 0.15 a2 0.0295 -- 0.0374 0.75 -- 0.95 b 0.0059 -- 0.0118 0.15 -- 0.30 4, 5 c 0.0031 -- 0.0091 0.08 -- 0.23 d -- 0.1181 bsc -- -- 3.00 bsc -- 2 e -- 0.1929 bsc -- -- 4.90 bsc -- e1 -- 0.1181 bsc -- -- 3.00 bsc -- 3 e -- 0.0197 bsc -- -- 0.50 bsc -- l 0.0157 0.0236 0.0315 0.40 0.60 0.80 l1 -- 0.0374 ref -- -- 0.95 ref -- parameter symbol min typ max units junction to ambient thermal impedance jedec 2-layer jedec 4-layer ja ja - - 170 100 - - c/w c/w 10l msop (3 mm body) package drawing ( note 1 ) e n 1 23 e b a1 a2 a d seating plane e1 1 l side view end view top view l1 c
cs2100-otp 26 ds841f2 10.ordering information the cs2100-otp is ordered as an un- programmed device. the cs2100-otp can also be factory programmed for large quantity orders. please see ?programming information? on page 24 for more details. 11.revision history product description package pb-free grade temp range container order# cs2100-otp clocking device 10l-msop yes commercial -10 to +70c rail cs2100p-czz cs2100-otp clocking device 10l-msop yes -10 to +70c tape and reel CS2100P-CZZR cs2100-otp clocking device 10l-msop yes automotive -40 to +85c rail cs2100p-dzz cs2100-otp clocking device 10l-msop yes -40 to +85c tape and reel cs2100p-dzzr cdk2000 evaluation platform - yes - - - cdk2000-clk release changes f1 updated period jitter specification in ?ac electrical characteristics? on page 7 . updated crystal and ref clock frequency specifications in ?ac electrical characteristics? on page 7 . added ?pll performance plots? section on page 8 . updated ?internal timing reference clock divider? on page 11 and added figure 8 on page 12 . removed clk_in skipping mode. removed auto r-mod. added mode pin toggle requirement to startup for cdk programmed devices to ?required power up sequencing for programmed devices? on page 19 . f2 updated to add automotive grade te mperature ranges and ordering options. contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com . important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual propert y rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve potential risks of death, per sonal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, au thorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclus ion of cirrus products in such appl ications is understood to be full y at the customer?s risk and cir- rus disclaims and makes no warranty, expres s, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom- er?s customer uses or permits the use of cirrus products in cr itical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any a nd all liability, including at- torneys? fees and costs, that may result fr om or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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